MPC10E-10c and MPC10E-15c
MPC10E comes in two variants, MPC10E-10c and MPC10E-15c, which can deliver 1Tbps and 1.5Tbps of throughput capacity, respectively. Each MPC10E supports different port speeds, including 400G, making it a true multi-rate or MRATE line card. Here is the summary of the speeds supported:
| Speed | MPC10E-10c | MPC10E-15c |
| 10GE | 40 (with 4x10GE Breakout) | 60 (with 4x10GE Breakout) |
| 25GE | 40 (with 4x10GE Breakout) | 60 (with 4x10GE Breakout) |
| 40GE | 10 | 15 |
| 100GE | 10 | 15 |
| 400GE | 2 | 3 |
Trio5 Architecture
Trio5 is a 500Gbps chipset in 16nm design. Just like previous generations, Trio5 is optimized for edge deployments. The built-in crypto engine is introduced for the first time in the Trio family. This enables inline MACSec at all port speeds starting from 10GE to 100GE. 400GE MACSec is possible through Trio6. Please refer to my blog on LC9600 to get more details.
Trio5 continues to support a large scale of advanced edge features supported in the previous revisions of Trio. The same has been discussed in detail in the LC480 TechPost. It supports a high number of queues and virtually unlimited firewall filters along with prefix lists and tunnels. It supports HQoS, Inline services such as NAT, 6RD, MAP-E, and Jflow/NetFlow along with telemetry, flex-filters and up to 16 label depth to enable advanced use cases of traffic engineering with segment routing (SR/SRv6).
rio5 is the packet forwarding engine or PFE in the MPC10E family of line cards. To optimize power and space many design considerations have been taken into account. First and foremost is the memory. Trio5 replaces the Hybrid Memory Cube (HMC) and in-house high-performance memory with High Bandwidth Memory (HBM), which is used for packet processing and WAN queuing systems. Another important difference from the previous version is the inclusion of HBM memory and Trio ASIC via a silicon interposer in 2.5D packaging design. This design reduces the bus length enabling better power performance and minimizes board area on the line cards. It helps in packing more Trio5 ASICS on a single-line card, thus improving the per-slot throughput by more than three times compared to line cards based on previous versions.
The Crypto engine has been introduced for the first time in the Trio family. It enables building power-efficient systems/line cards that won’t require an external component such as PHY to secure the ethernet connections between routers and switches.
The size of on-chip memory (OCMEM) in Trio5 has been increased, which is used for on-chip delay bandwidth buffers and the WAN queuing functions.
High Bandwidth Memory (HBM) is used as off-chip memory for delay bandwidth buffer and high scale flow table (Jflow) storage.
Each Trio5 has the following main components:
1- Lookup SubSystem (LUSS) provides all packet processing functions such as route/label lookup, firewall, and multi-field packet classification. This subsystem holds an array of Packet Processing Engines (PPE) to perform these functions. Trio5 and Trio4 each have 96 PPE, but they run at a higher clock frequency to handle the increase in throughput in Trio5.
2- Memory and Queuing SubSystem (MQSS) provides data paths and rich queuing functionality. It acts as an interface between WAN and Fabric. It has a pre-classifier where packets are classified as low/high priority. Unlike initial generations of Trio where an eXtended Queuing SubSystem (XQSS) was used to provide rich queuing functionality, Trio5 integrates this function within the MQSS block. This helps in the reduction of foot print and improves the power performance without any compromise on functionality.
3- HBMIF is the interface to HBM mem and on-chip FlexMem
4- FlexMem is the on-chip memory that is used for WAN queuing data structures and on-chip delay bandwidth storage.
Life of Packet inside Trio5
The life of the packet inside Trio5 is similar to the one described in Trio6 TechPost
